Vhdl Program For Parity Generator

I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to compile it successfully. My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for. The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even. My code is written such that a basic XOR block is then added as a component of the complete parity generator.

Odd Parity Generator - Testbench--- This structural code instantiate the ODD_PARITY_TB module to create a --- testbench for the odd_parity_TB design. The processes in it are the ones--- that create the clock and the input_stream.Explore the design in the --- debugger by either adding to the testbench to provide stimulus for the. Theory of Parity Generator: A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors.

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Browning 1900 serial numbers. I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do. I thank you all in advance and look forward to any input, good or bad.

Basic XOR gate block VHDL Code library ieee; use ieee.std_logic_1164.all; entity xor_gate is port( a: in std_logic; b: in std_logic; pari: in std_logic; paro: out std_logic); end xor_gate; architecture behavior of xor_gate is begin paro. As mentioned in the comments the or part of your 'xor_gate' prevents it from actually working as an xor gate to calculate bit parity.

Instead your paro signal will be '0' when a=b and '1' when a/=b (the 16 bit vectors, not the bits within xor_gate). If that was your intended functionality, then paro.